1. Field of the Invention
The present invention relates to a failure self-diagnosis device for semiconductor memory, in particular, a failure self-diagnosis device for semiconductor memory, which is used for an IC tester on which a multi-bit semiconductor memory having a large capacity is mounted.
2. Description of the Related Art
FIG. 5 is a construction view showing a typical conventional failure self-diagnosis device for semiconductor memory, for example, which is disclosed in U.S. Pat. No. 5,271,015 corresponding to Japanese Patent Application No. Tokukai-Hei 4-178580. As shown in FIG. 5, the device comprises: (a) a CPU 51 into which a sequence program for a diagnosis is written; (b) a clock generating circuit 56 which is started by a test start signal TST of the CPU 51; (c) a data generating circuit 52 which is operated by an output CLKa of the clock generating circuit 56, for generating data to be written by a memory 55 when the CPU 51 sets a memory writing mode (a signal WMD is "H"), and for generating expected data when the CPU 51 sets a memory reading out mode (a signal WMD is "L"); (d) an address generating circuit 53 which is operated by an output CLKa of the clock generating circuit 56, for generating an address assigning signal to write the data generated by the data generating circuit 52 into a predetermined address of the memory 55 when the CPU 51 sets a memory writing mode, and for generating an address assigning signal to read out data from the predetermined address of the memory 55 when the CPU 51 sets a memory read out mode; (e) a test finish detecting circuit 57 which is operated by the output CLKa of the clock generating circuit 56, for detecting that a test of the memory 55 is finished, and for generating a test stop signal TSP to stop an operation of the clock generating circuit 56; (f) a switching circuit 58 for inputting the data generated by the data generating circuit 52, for outputting an input data as an input data MID of the memory 55 when the CPU 51 sets the memory writing mode, and for outputting an input data as an expected data EXD when the CPU 51 sets the memory reading out mode; (g) a comparator 54 for inputting a read out data MOD of the memory 55 as a first input and an expected data EXD of the memory 55 as a second input, to compare the read out data MOD of the memory 55 with the expected data EXD, and for detecting coincidence or non-coincidence between the expected data EXD and the read out data MOD to judge whether the memory 55 is normal or failed; and (h) a flip flop (hereinafter, referred as to "FF") 59 which inputs an output CMP of the comparator 54 as a set signal and the test signal TST of the CPU 51 as a reset signal, for outputting a failure signal when the set signal is inputted.
When the CPU 51 sets the memory writing mode (the signal WMD is "H"), a write enable signal MWT to be outputted to the memory 55 is generated by a NAND circuit 60 by synchronizing with the output CLKb (having a phase which is different from that of the signal CLKa) of the clock generating circuit 56.
In the above-described device, the self-diagnosis of the memory 55 is carried out as follows.
The CPU 51 sets the writing mode (the signal WMD is "H"). The CPU 51 sets initial data values for the data generating circuit 52 through a data bus DTB, and sets initial address value for the address generating circuit 53 therethrough. Further, the CPU 51 sets a test finish condition for the test finish detecting circuit 57. Sequentially, the CPU 51 outputs the test start signal TST to the clock generating circuit 56 in order to start it.
The clock generating circuit 56 generates the clock signals CLKa and CLKb having phases which are different from each other. The data generating circuit 52, the address generating circuit 53 and the NAND circuit 60 are operated by synchronizing with the clock signals CLKa and CLKb in order to write the data generated by the data generating circuit 52 into the address of the memory 55, which is assigned by the address assigning signal generated by the address generating circuit 53.
When the memory writing operation in which the data was written into an address region to be tested was finished, the test finish detecting circuit 57 detects the finish of the memory writing operation and generates the test finish signal TSP to stop the clock generating circuit 56.
Next, the CPU 51 sets the reading out mode (the signal WMD is "L"). Similarly to the writing mode, the CPU 51 sets initial data values for the data generating circuit 52 through the data bus DTB, and sets initial address value for the address generating circuit 53 therethrough. Further, the CPU 51 sets the test finish condition for the test finish circuit 57. Sequentially, the CPU 51 outputs the test start signal TST to the clock generating circuit 56 in order to start it, and outputs the signal TST to the FF 59 in order to reset it.
The clock generating circuit 56 generates the clock signals CLKa and CLKb having phases which are different from each other. The data generating circuit 52 and the address generating circuit 53 are operated by synchronizing with the clock signal CLKa in order to read out the data from the address of the memory 55, which is assigned by the address assigning signal generated by the address generating circuit 53 and in order to read out the expected data EXD generated by the data generating circuit 52. The comparator 54 compares the expected data EXD with the data MOD which is read out from the memory 55 in sequence. As a result that the comparator 54 compares two data, when two data are not coincident with each other and the comparator 54 detects the failure of the memory 55, the FF 59 is set by the comparison result signal CMP.
When the data read out operation in which the data is read out from the address region to be tested, of the memory 55 and the comparing operation in which the comparator 54 compares the expected data EXD with the data MOD, are finished, or when the comparator 54 detects the failure of the memory 55, the test finish detecting circuit 57 detects the finish of the data readout operation and the comparing operation. Then, the test finish detecting circuit 57 generates the test stop signal TSP to stop the clock generating circuit 56 and the test is finished.
The diagnosis of the memory 55 can be carried out by examining the output of the FF 59 through a tester pin when the test is finished.
However, because the conventional self-diagnosis device for semiconductor memory has the above-described construction, there are the following problems. In the self-diagnosis of the memory, when the failure does not occur, the self-diagnosis can be carried out at high speed. On the other hand, when the failure occurs at a plurality of addresses, so that the set signals are outputted to a plurality of tester pins, it is necessary to test the memory the same number of times that the self-diagnosis device detects the failures, in order to search the tester pin corresponding to the failed address and the address at which the failure occurs. As a result, it takes a long time to test the memory.